Modulators and Demodulators
- FSK
- PSK
- QAM
- FHSS
- CDMA
- OFDM
FSK:
The Mary FSK Demodulator IP core
is a precision FSK demodulator based on a non-coherent receiver design.
The demodulator is programmable to select different tone frequencies.
Each local oscillator is implemented as a DDS. After mixing, the I and
Q signal paths for each tone are to remove components other than tone
frequencies. The characteristics of filters are also programmable.
Input data samples may be either complex or real and support for both
passband and baseband signals is provided.
The IP core uses a single clock for synchronous design purposes. The sub-blocks are highly optimized for FPGA implementation.
PSK:
The Mary PSK Demodulator IP core
is designed to demodulate BPSK, QPSK, 8PSK, OQPSK and π/4 QPSK
modulation schemes. The Demodulator performs carrier recovery using
Costas loop and Symbol Timing Recovery using a matched filter based
timing recovery. Design includes Square Root raised cosine filtering
with the desired Roll-off factor. The In-phase and quadrature outputs
are mapped using the De-mapper based on the selected modulation.
The IP core uses a single clock for synchronous design purposes. The sub-blocks are highly optimized for FPGA implementation.
QAM:
The QAM Demodulator IP core
has been designed to lock robustly in the presence of noise, frequency
& timing offsets, static & dynamic multi-path channels and
various other forms of interference. In the block diagram shown below,
the resampler module is responsible for generating down-converted and
filtered samples of the QAM input signal. The symbol timing error
estimator module is responsible for generating correctly timing
constellation samples of the baseband & filtered signal by
performing channel filtering; symbol rate detection and timing error
estimation. The equalizer and carrier recovery module is responsible
for generating the original QAM constellation by performing carrier
frequency recovery; channel acquisition, equalisation & tracking
and DC offset correction. The IP core uses a single clock for synchronous purposes. The architecture is highly optimized for FPGA implementation.
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